VHDL-Jackpot-Machine-on-FPGA-Board
A three-digit jackpot machine using synchronous counters, multiplexing, and state machines. When three independent 3-bit counters are running and you press buttons to stop them individually, the system checks if all three digits are equal. If they are, the 7-segment display flashes rapidly, and RGB LEDs light up to indicate your jackpot win.
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