Research and develop novel accelerator architectures for LLM inference, focusing on binary and ternary weights, model-specific computation, and efficient data movement.
Explore how model weights and operations can be encoded directly into silicon, and how much hardware can be reused across different models.
Investigate trade-offs across model quality, inference latency, throughput, silicon area, and power consumption.
Design and evaluate compute architectures, memory hierarchies, attention mechanisms, KV-cache systems, and low-precision arithmetic.
Explore automated approaches to translating model architectures and trained weights into efficient hardware, including compiler-driven RTL generation.
Build architectural simulators, performance models, and FPGA prototypes to validate ideas before committing to silicon.
Work closely with our founders and ASIC engineers to turn promising research into implementable microarchitectures.
Help define the longer-term technical direction of Lamb Labs' inference hardware.
What we're looking for
A strong research or engineering background in computer architecture, digital hardware, AI accelerators, or hardware–software co-design.
Ideally a PhD or equivalent research experience in computer engineering, electrical engineering, computer science, or a related field.
Experience designing, implementing, or evaluating hardware accelerators for neural networks or other computationally intensive workloads.
A deep understanding of digital architecture, including datapaths, pipelining, parallelism, memory systems, and data movement.
Familiarity with RTL design and verification.
The ability to take an open-ended research problem, develop a hypothesis, build a prototype, and evaluate it quantitatively.
Strong programming skills and comfort working across software, architecture, and hardware.
The curiosity to challenge established approaches and the engineering discipline to distinguish promising ideas from impractical ones.
Comfort using AI tools to accelerate research, development, and experimentation.
Especially useful experience
Research or practical work involving:
LLM or transformer accelerators, including attention and KV-cache optimisation.
Binary, ternary, or other low-precision neural networks.
Model compression, quantisation, sparsity, or inference optimisation.
Hardware generation, compilers, XLS, or automated RTL generation.
FPGA-based neural network acceleration.
Compute-in-memory, near-memory computing, or hardwired neural network architectures.
A PhD is not a strict requirement. We're more interested in exceptional technical ability, original thinking, and evidence that you can turn ideas into working systems.
Why join
You'll help invent a new approach to AI inference hardware from its earliest stage.
Rather than optimising an existing processor architecture, you'll have the opportunity to rethink fundamental assumptions about how neural networks should be implemented in silicon.
You'll work directly with the founders, have meaningful ownership over architectural decisions, and see your ideas progress from research to physical chips.
We're a small team moving quickly on a technically ambitious problem. We care about independent thinking, rigorous experimentation, and building things that work.
We're currently based in San Francisco and London.
Source: Y Combinator job 116541. Listed on YC when retrieved 2026-11-02.
